Semiconductor memory systems are subject to errors. That is, data retrieved from the memory does not always match data that was originally written to the memory. Such errors can be caused by stray alpha particles, damage to the memory devices or by a variety of operating conditions, such as power supply fluctuations, noise, etc. Regardless of the source, such errors are clearly undesirable. Consequently, most modern memory systems include error is detection and/or error correction capabilities.
Typical approaches to detecting and correcting errors in memory rely upon some form of error correction code to identify and correct such data errors. Such error correction codes typically include a mathematical algorithm that is applied to the data to be checked and corrected, and additional error correction code ("ECC") bits. Usually, the ECC bits are stored in a separate memory dedicated to the ECC bits. The amount of memory dedicated to storing the ECC bits can be significant. For example, the memory overhead for the ECC bits can often exceed 10%.
The amount of ECC bits required can depend upon the type of error correction code being utilized. In some applications, very little or no error correction is desired. For example, in video games, occasional image data errors are unlikely to significantly affect the images perceived by a user. Rather than devote processor power to error correction calculations and memory to ECC bits, such applications largely ignore image data errors to increase the speed of play.
Such applications will be referred to herein as error tolerant applications. Error tolerant applications typically use no error correction calculations or limited error correction algorithms that require little or no ECC memory.
Other applications can tolerate little or no data errors. For example, data errors can be extremely undesirable in accounting programs. Such applications will be referred to herein as error intolerant applications. Error intolerant applications usually utilize robust error correction algorithms requiring a substantial amount of ECC memory.
Typically, memory devices for storing ECC bits are segregated from memory devices for conventional data. For example, 144 pin 4-MB.times.64 double in-line memory module ("DIMM") not used to store ECC bits could be implemented using 16 4-MB.times.4 dynamic random access memories ("DRAMs"). However, the same data storage capacity plus the capacity to store ECC bits would require a 4-MB.times.72 DIMM implemented using 18 4-MB.times.4 DRAMs. Thus, implementing ECC requires two additional DRAMs.
One problem with such memory architectures is that they do not fully utilize the available memory capacity. For example, error tolerant applications do not need nor use the extra memory provided to store ECC bits. Thus, valuable memory capacity is left unused. In the above example, 11% of the DRAMs on the DIMM are wasted when the DIMM is not used to store ECC bits.
On the other hand, error intolerant applications require more memory and are often limited by the amount of available ECC memory. Consequently, the speed with which the application runs can be increased by increasing the amount of available ECC memory. Adding such memory can be costly. Moreover, adding such memory capacity increases the amount of unused memory in error tolerant applications.